using sbt should be considered a form of self-harm

i wanted to give scala a fair try because vexriscv is just an incredibly good CPU, but it immediately loses twice as many points as it ever had for being fuckin impossible to build

can you guess what this error message is attempting to communicate

bonus points for being a tex-style "the normally exclusively batch tool dislikes something and as a result it goes interactive and presents you with a prompt with four choices, none of which do anything desirable" (and because the JRE takes a while to exit, if you press "q" twice the second one will get stuck in your shell input buffer)

@whitequark Are there any Java-ecosystem build tools that are anything other than awful?

I basically feel like every time I try to deal with anything in the Java ecosystem, I'm in a world of hurt because of overly complicated, cumbersome tooling.

@unlambda pretty much

@whitequark what kind of behavioral therapy is “sbt”?

@c0dec0dec0de scala ball torture (jokes on them i don't have balls. unfortunately joke's also on me because it's still torture ime)

@whitequark one of:

• it should have been sbt run root
• git modules not checked out
• network racconnectivity error while feting dependencies
• your java is the wrong version™
• classpath issues

@charlotte i'm doing

sbt "runMain xxx.GenCpu"

where xxx is a package in the current project

@whitequark hmm maybe the quotes are wrong? idk

@charlotte i'm copying the invocation from the README, except i don't want to modify the source of vexriscv, i want to use it as a submodule

@whitequark idk, sorry. extremely unhelpful error though

after 40 minutes of pain i managed to write a build.sbt that works. i don't understand why it works and i didn't expect it to, i just permuted it in a manner i found amusing. none of the tutorials and docs i found appear to be explaining this behavior

i... i'm going to take it while i'm ahead i think

@bob to my head, yeah

[i know what nailgun is]

@whitequark I’m actually a big fan of SpinalHDL, but sbt is ridiculous. It’s one place where a LLM might help because the build definition API was stochastically generated too!

@craigjb I asked ChatGPT and the result was completely unhelpful too

@whitequark Lovely! There are so many footguns with sbt and scala builds, it’s dumb. Once I had a working environment, I’ve held onto it and cloned.

Recent things I’ve run into:
- Scala version defined for the project, but it wasn’t a special global thing with a / so it didn’t apply everywhere
- I didn’t manually exclude a local dependency from being looked up in maven, still not sure on this one…

Cont…

@whitequark
- When you include a local dependency, e.g. a vexriscv checkout, some of the build.sbt comes with it, some doesn’t. Then I have to manually tell it to not look for the maven version… idk
- Using scala > 2.12 with SpinalHDL = not fun sbt errors I couldn’t figure out
- I added the spinal DSL compiler plugin, but it wasn’t on the right project in sbt. I put it on the library I’m making, but it needed to be on the project that uses it. Still figuring that out too….

@whitequark SpinalHDL once all the build shit is figured out, is quite nice!
I guess python has its own distribution and packaging pains, but you’re an expert. I used to use python more and fight that fight too—especially Cython stuff…
Scala definitely does not making onboarding easy though. It’s a shame

@craigjb I haven't formed an opinion on Scala or SpinalHDL yet (besides the like. racist incidents in Scala circles, but I still want to have a technical opinion on it too)

@whitequark I hope scala will eventually come to the same conclusion as the python community that the metadata should not be in code, but statically defined. Like a scalaproject.toml or something…

@whitequark I wasn’t aware of that… I’m not plugged into the Scala community at all though.
Also docs are not a strong point yet for Spinal. The libraries have lots of good stuff, just source-reading required. Anyway, not trying to be a shill. I’ve just been using it a lot for recent projects.

This project has VexRiscv with Rust Embassy on it to handle USB keyboard, HDMI detection state machine, etc. HDMI RX using GTPs in Spinal too. Embassy on VexRiscv was a great experience!

@craigjb I am very impressed with VexRiscv and it single-handedly convinced me that I need to really look into Scala & Spinal

@craigjb it's basically the only non-Amaranth HDL piece I use in my own work; if that's not indicative of its quality I don't know what is

@whitequark Charles (Dolu1990) is such a helpful person too.
For Amaranth, it’d be cool to auto-generate SVDs for RiscV systems too. I’m working on a library for spinal to generate an SVD from my peripheral bus attachments, then generate the PAC, and even an Embassy HAL for library peripherals. I’m afraid I’m not much an Amaranth guy yet (I know…), but I assume there’s a register definition interface to capture register field definitions. SpinalHDL has one called RegIf. I added SVD out for Rust.

@craigjb there's an amaranth-soc interface which has CSR definitions, but SVD is not upstream yet (you do get JSON though); however the Tiliqua project has a working Rust SVD interface. it's something I'd really like to improve as it's been a neglected area for a while and we unfortunately lost (AWOL) a lead developer...

@whitequark this might already exist in amaranth and im just ignorant.

@craigjb I'm working on a little SoC for myself rn so I have all this stuff generally in my mind at the moment, even

@whitequark It’s kind of a fun little design space. I went halfway down the path of creating a more general interconnect generator, so you could define the CPU bus connectivity, peripheral buses, and bridges in a tree, then a separate build step would use whatever concrete buses you pick (AXI, APB, Wishbone, etc).
Turns out I just use AXI and APB for everything in my SoCs though. So I just chopped all the complexity off and did the simple thing.

@craigjb yeah, we've done similar stuff in Amaranth SoC and hit the problem too (except with more Wishbone, which, yuck.)

@whitequark With a tree representation, edges could encode things like latency requirements, so the builder would know where to pipeline vs. not. I’m not sure it’s worth finishing though. My simple AXI+APB generator would fit as a nice layer on top, I’m just not sure how common it is for people to mix and match buses.

@whitequark The tree could also help where you could generate different versions with different pipeline stage configs and implement in parallel to explore timing. I’ve done that manually before. Vivado is so single-core heavy that spawning multiple parallel runs to explore doesn’t really take more time.

@whitequark *reaches under desk for strace while maintaining eye contact*

> sbt (originally simple build tool, nowadays stands for nothing[4])

Thanks Wikipedia ...wait. oh. Oh no.

@whitequark

@whitequark In a way, I really wish Vex wasn't written in Scala; but that being said, as someone currently building a DAG dependency graph so my SystemVerilog LSP can understand what order to compile documents in... I don't know if it's any better.

@mlyoung lord no i would not use Verilog for anything at all