stares i do not like that this instruction set has both "reset device" and "device reset" opcodes and they have non-trivially different semantics

stares harder this datasheet defines the values for bits ID7-ID0 and bits ID15-ID0 and the implied values for ID7-ID0 (via ID15-ID0) differ from the express values for ID7-ID0

"for more information please re-read"

did the Scarfolk Council fund the development of this chip

edit: oh, no, they have a separate "DTR datasheet" (where they also describe non-DTR QPI instructions?..)

i found the DTR datasheet and it describes STR instructions as well. i cannot comprehend why are there two different documents describing the exact same flash.

you would think the five tables called "instruction set table" describe five instruction sets. you would be wrong. tables 1, 2, and 4 describe the first instruction set, tables 3 and 5 describe the second instruction set. (there's a volatile and a non-volatile mode bit to switch between the two)

@whitequark My mind is now combining the AliExpress motherboard gacha you shared the other day with this to create AliExpress ISA gacha. "Our supplier switched from <X> to RISC-V part way through and didn't tell us", or "our supplier changed what fuses they set because they didn't think it mattered (it does)".

(The latter could be 'now it boots in a different ISA mode than it did before but the right boot chain could switch back".)

@cks terrifyingly, the material conditions for this exist and all it would take is one adventurous reseller...

this is why https://crackhead.technology exists

@whitequark does one of them reset the device controller and the other one clear any stored data?

@whitequark Yeah the long one is RDID (the one we'd usually use these days if not SFDP), the short one is REMS... but yeah i can see the funny.

@whitequark I am confused whether it is the exact same or not. Do these tiny notes in the ordering info mean part numbers ending Q don’t support DTR?

@rebelmike eagle eyes! thank you

although in my opinion this makes it even worse somehow lmao

@whitequark It is super unclear. I actually have both versions knocking about, so I could do a test, but so far I haven’t used DTR mode.
What I do know is the continuous mode bits for quad fast read that are only documented in the DTR datasheet do work on both.

@rebelmike I'd be super curious if they're binning things like that or if it's two different devices somehow

(although even a test wouldn't be quite conclusive because it is not beyond silicon vendors to package a completely different SKU under the same name for market segmentation reasons...)

@rebelmike @whitequark

You take the Q-option if you want to make sure that you can use quad mode without programming the status register -- and also the chip will not interpret those I/O lines as WP or HOLD so you don't need to put pullups/pulldowns on them... ehh (maybe this matters for some ROM bootloader?..).

(And you don't take it if you're using WP and/or HOLD in your circuit, of course.)

@urja @rebelmike yes but it's also talking about the "new device ID" / "family", no?

@whitequark @rebelmike

Oh yeah those are a bit confusing that they're mixing up the families into it.
... like, what family is it if there's neither special option?

Also of note for anyone casually reading this, DTR and QPI are different from the normal QE=1 quad mode

(DTR being well, "pooh, you're making a bad copy of the DDR RAM interface" :P - and QPI being a mode that uses quad mode for everything, including commands.)

@whitequark So, sample size of 1, but my Q part does a "DTR Fast Read Quad I/O (EDh)" just the same as the M part.

@rebelmike thank you, much appreciated!