nytpu the wyvern
nytpu@tilde.zone
Hmm, thinking about bit order for my CPU ISA's instructions again…
Which do you prefer for fixed-length 32-bit instructions? (No affect on actual decoding or anything)
1. Fields ordered from MSB to LSB, so they read in a logical order when looking at diagrams and reading instructions written out in the normal right-to-left way of writing numbers (with the LSB at the right), but "backwards" when looking at real code in hex dumps
2. Fields ordered from LSB to MSB, so they read better in hexdumps (easy to pick out the predication condition nibble and ALU op nibble at neatly aligned addresses, etc.), but conceptually feel "backwards" when looking at diagrams and written out instructions
(Not conveyed very well but people experienced probably get what I mean)
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@nytpu I feel like I am not understanding your question, but
If the operands are ordered in a logical way in the assembly -- by which I mean The Glorious ARM and MIPS way instead of The Barbarous AT&T x86 way -- then I'm good
Because I'm not hex dumping the actual code at all
-- being used to x86, where the hex dump is completely unreadable by a non-Intel-employee anyway. And they still probably need manuals at their side most times
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Charlotte 
/Cinny 
charlotte
instead of The Barbarous Intel way
if you mean opcode destination, source that is also the intel way
on unix and derivatives it’s reversed because on the PDP11 it’s opcode source, destination and AT&T decided that for its port of unix to the x86 isa they would do the same thing for the assembler
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Charlotte /Cinny
charlotte
@jhwgh1968 @nytpu as far as for how the hexdump goes
it only makes sense to do that if the isa is big endian, because the bytes get reversed anyways in little endian
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nytpu the wyvern
nytpu@tilde.zone@jhwgh1968 That's why I specified fixed-length instructions, where you can reliably see the instruction boundaries and stuff
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nytpu the wyvern
nytpu@tilde.zone@jhwgh1968 And I guess I mean, should I "optimize" the way it's written for documentation diagrams and such or looking at raw hex dumps (for some reason, not common for me)
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J. "Henry" Waugh
jhwgh1968@chaos.social@nytpu yeah, and a better way to state my point was:
I never look at hex dumps *in general* -- because Intel trained me they're not worth my effort, and I carry that forward to other saner architectures too. I always go find a disassembler and have it tell me what they say
So in terms of your priorities and considerations, big picture, that is how I "use" a new architecture
Which I suppose means that documentation diagrams would be better
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J. "Henry" Waugh
jhwgh1968@chaos.social@charlotte I thought Intel started putting destination last on some of their extensions, but doing a quick check of diagrams it seems my memory was incorrect
I will (playfully) repair my slander
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Charlotte /Cinny
charlotte
@jhwgh1968 @nytpu given how many different assembly languages have been made for intel cpu isas i’m glad the same doesn’t happen for the others
see also the intel 8080 which has a different assembly language from the z80 (which is for the most part just an extension of the i8080)
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@charlotte @jhwgh1968 (My ISA is Harvard architecture and the lowest addressable unit of the instruction bus is the instruction size, so the endian consideration is only how it's stored on disk and in which case the bit order is as important of a consideration. And the FPGA core expects a 32-bit ported RAM interface for the instruction bus)
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@jhwgh1968 (In the second case for ARM32, I can actually tell that all those instructions are al/always conditional due to the leading e)
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