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Charlotte 🦝 therian

The larger nop encodings on the 6502 and x86 have an ineffective address
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Meanwhile RISC architectures have a nop encoding space, riscv32i has almost 3 million nops
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Riscv assembler that instead of using the canonical nop addi zero, zero, 0, uses a completely random nop instruction
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@charlotte Are they always NOPs or is it implementation defined NOPs?
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@erk they are NOPs because the operations they correspond to have no effect (stuff like writing the result to the zero register, arithmetic/logic instruction with an identity operand, fences that have no effect, etc)
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@erk riscv has one canonical nop, and the other nop encodings correspond to hints, most of which are currently unassigned
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@charlotte i once saw an implementation for a data output port that used the 32 nops of the 65c02 to output 5 bits of data at blazingly fast rates
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@miifox on the 65c816 you can use the WDM instruction for that, $42 followed by the byte you want to transmit. takes 2 cycles to execute

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@charlotte yeah nopblasting takes 1 cycle so still 12.5% faster!
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@miifox if you allow overwriting the accumulator, the 65c816 is faster if you blast it with 16 bit lda instructions

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@miifox i mean the 65c816 is faster in general, 65c02 goes to 14MHz, 65c816 goes to 20MHz

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